1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, a MOSFET and a method for manufacturing the same.
2. Description of the Related Art
First a conventional LDD (lightly doped drain) transistor will be described. A gate oxide film is formed on the surface of a P-type silicon substrate, a gate electrode is formed on the gate oxide film, and sidewalls of SiO.sub.2 are formed on both sides of the gate electrode by CVD (chemical vapor deposition). Ions are implanted into an LDD region, using the gate electrode as a mask, to form an N.sup.- -type layer in the P-type silicon substrate, and ions are implanted into a source/drain region, using the gate electrode and the sidewalls as masks, to form an N.sup.+ -type layer in the P-type silicon substrate.
In the LDD transistor, even though a high voltage is applied to the drain side, a drain electric field is mitigated by the N.sup.- -type layer of the LDD region. Therefore, impact ionization is suppressed in the vicinity of the drain region, and hot carriers are reduced, resulting in high reliability of the transistor.
Since, in the LDD transistor described above, the ion concentration of the N.sup.- -type layer of the LDD region is low, the parasitic resistance is higher than that of a normal transistor, with the result that the LDD transistor deteriorates in driving performance. In order to prevent the driving performance from deteriorating, an LDD transistor having sidewalls formed of materials having a high dielectric constant, such as SiN, is proposed.
In the conventional LDD transistor, the electric field of the surface of the N.sup.- -type layer is strengthened by the sidewalls formed of materials having a high dielectric constant. The concentration of electrons of the N.sup.- -type layer is increased, and the parasitic resistance thereof is lowered. In this case, however, a gate fringing electric field is increased, and a large gate parasitic capacitance is generated between the gate electrode and the N.sup.+ -type layer of the source/drain region, thereby causing a drawback wherein the driving performance of the transistor is decreased and the power consumption thereof is increased.